Logic and computer design fundamentals (Record no. 10814)
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000 -LEADER | |
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fixed length control field | 10265nam a2200265 a 4500 |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
ISBN | 0130124680 |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
ISBN | 9780130124685 |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
ISBN | 8178083345 |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
ISBN | 9788178083346 |
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
Classification number | 004.2 |
Item number | MAN |
100 ## - MAIN ENTRY--AUTHOR NAME | |
Personal name | Mano, M.Morris ; |
245 ## - TITLE STATEMENT | |
Title | Logic and computer design fundamentals |
250 ## - EDITION STATEMENT | |
Edition statement | 2nd Edition |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
Place of publication | New Delhi : |
Name of publisher | Pearson Education Asia, |
Year of publication | 2001. |
300 ## - PHYSICAL DESCRIPTION | |
Number of Pages | xvi, 650 p. : |
Other physical details | illustrations ; |
500 ## - GENERAL NOTE | |
General note | Included Index. |
505 ## - FORMATTED CONTENTS NOTE | |
Formatted contents note | Digital Computers and Information 3 --<br/>1-1 Digital Computers 3 --<br/>Information Representation 5 --<br/>Computer Structure 6 --<br/>More on the Generic Computer 6 --<br/>1-2 Number Systems 8 --<br/>Binary Numbers 9 --<br/>Octal and Hexadecimal Numbers 10 --<br/>Number Ranges 12 --<br/>1-3 Arithmetic Operations 13 --<br/>Conversion from Decimal to Other Bases 15 --<br/>1-4 Decimal Codes 17 --<br/>BCD Addition 19 --<br/>1-5 Alphanumeric Codes 20 --<br/>ASCII Character Code 20 --<br/>Parity Bit 22 --<br/>Combinational Logic Circuits 27 --<br/>2-1 Binary Logic and Gates 27 --<br/>Binary Logic 28 --<br/>Logic Gates 30 --<br/>2-2 Boolean Algebra 31 --<br/>Basic Identities of Boolean Algebra 33 --<br/>Algebraic Manipulation 35 --<br/>Complement of a Function 38 --<br/>2-3 Standard Forms 39 --<br/>Minterms and Maxterms 39 --<br/>Sum of Products 43 --<br/>Product of Sums 44 --<br/>2-4 Map Simplification 45 --<br/>Two-Variable Map 46 --<br/>Three-Variable Map 47 --<br/>Four-Variable Map 52 --<br/>2-5 Map Manipulation 55 --<br/>Essential Prime Implicants 55 --<br/>Nonessential Prime Implicants 57 --<br/>Product-of-Sums Simplification 58 --<br/>Don't-Care Conditions 60 --<br/>2-6 Nand and Nor Gates 62 --<br/>Nand Circuits 64 --<br/>Two-Level Implementation 65 --<br/>Multilevel Nand Circuits 67 --<br/>Nor Circuits 69 --<br/>2-7 Exclusive-Or Gates 71 --<br/>Odd Function 73 --<br/>Parity Generation and Checking 74 --<br/>2-8 Integrated Circuits 76 --<br/>Levels of Integration 76 --<br/>Digital Logic Families 76 --<br/>Positive and Negative Logic 79 --<br/>Transmission Gates 81 --<br/>Combinational Logic Design 91 --<br/>3-1 Combinational Circuits 91 --<br/>3-2 Design Topics 92 --<br/>Design Hierarchy 93 --<br/>Top-Down Design 96 --<br/>Computer-Aided Design 96 --<br/>Hardware Description Languages 97 --<br/>Logic Synthesis 99 --<br/>3-3 Analysis Procedure 100 --<br/>Derivation of Boolean Functions 101 --<br/>Derivation of the Truth Table 102 --<br/>Logic Simulation 103 --<br/>3-4 Design Procedure 105 --<br/>Code Converters 107 --<br/>3-5 Decoders 111 --<br/>Decoder Expansion 113 --<br/>Combinational Circuit Implementation 114 --<br/>3-6 Encoders 116 --<br/>Priority Encoder 117 --<br/>3-7 Multiplexers 119 --<br/>Combinational Circuit Implementation 122 --<br/>Demultiplexer 124 --<br/>3-8 Binary Adders 125 --<br/>Half Adder 125 --<br/>Full Adder 126 --<br/>Binary Ripple Carry Adder 127 --<br/>Carry Lookahead Adder 129 --<br/>3-9 Binary Subtraction 132 --<br/>Complements 134 --<br/>Subtraction with Complements 135 --<br/>3-10 Binary Adder-Subtractors 137 --<br/>Singed Binary Numbers 138 --<br/>Signed Binary Addition and Subtraction 140 --<br/>Overflow 142 --<br/>3-11 Binary Multipliers 144 --<br/>3-12 Decimal Arithmetic 145 --<br/>Use of Complements in Decimal 147 --<br/>3-13 HDL Representations --<br/>VHDL 148 --<br/>Structural Description 150 --<br/>Dataflow Description 153 --<br/>Hierarchical Description 155 --<br/>Behavioral Description 157 --<br/>3-14 HDL Representations --<br/>Verilog 159 --<br/>Structural Description 160 --<br/>Dataflow Description 161 --<br/>Hierarchical Description 165 --<br/>Behavioral Description 165 --<br/>Sequential Circuits 183 --<br/>4-1 Sequential Circuit Definitions 184 --<br/>4-2 Latches 186 --<br/>SR and S R Latches 187 --<br/>D Latch 190 --<br/>4-3 Flip-Flops 191 --<br/>Master-Slave Flip-Flop 192 --<br/>Edge-Triggered Flip-Flop 195 --<br/>Standard Graphics Symbols 197 --<br/>Characteristic Tables 199 --<br/>Direct Inputs 200 --<br/>4-4 Sequential Circuit Analysis 201 --<br/>Input Equations 201 --<br/>State Table 202 --<br/>Analysis with JK Flip-Flops 206 --<br/>State Diagram 206 --<br/>4-5 Sequential Circuit Design 208 --<br/>Design Procedure 208 --<br/>Finding State Diagrams and State Tables 209 --<br/>4-6 Designing with D Flip-Flops 214 --<br/>Designing with Unused States 215 --<br/>4-7 Designing with JK Flip-Flops 218 --<br/>Flip-Flop Excitation Tables 218 --<br/>Design Procedure 219 --<br/>4-8 HDL Representation for Sequential Circuits --<br/>VHDL 224 --<br/>4-9 HDL Representation for Sequential Circuits --<br/>Verilog 232 --<br/>Registers and Counters 249 --<br/>5-1 Definition of Register and Counter 249 --<br/>5-2a Registers 250 --<br/>Register with Parallel Load 251 --<br/>5-3 Shift Registers 253 --<br/>Serial Transfer 254 --<br/>Serial Addition 256 --<br/>Shift Register with Parallel Load 258 --<br/>Bidirectional Shift Register 260 --<br/>5-4 Ripple Counter 261 --<br/>5-5 Synchronous Binary Counters 263 --<br/>Design of Binary Counters 264 --<br/>Counter with D Flip-Flops 267 --<br/>Serial and Parallel Counters 268 --<br/>Up-Down Binary Counter 269 --<br/>Binary Counter with Parallel Load 270 --<br/>5-6 Other Counters 273 --<br/>BCD Counter 273 --<br/>Arbitrary Count Sequence 274 --<br/>5-7 HDL Representation for Shift Registers and Counters 276 --<br/>5-8 HDL Representation for Shift Registers and Counters 278 --<br/>Memory and Programmable Logic Devices 285 --<br/>6-1 Memory and Programmable Logic Device 285 --<br/>Definitions 286 --<br/>6-2 Random-access Memory 287 --<br/>Write and Read Operations 289 --<br/>Timing Waveforms 290 --<br/>Properties of Memory 292 --<br/>6-3 RAM Integrated Circuits 292 --<br/>Three-State Buffers 296 --<br/>Coincident Selection 297 --<br/>Dynamic RAM ICs 301 --<br/>6-4 Array of RAM ICs 307 --<br/>Arrays of Dynamic RAM ICs 310 --<br/>6-5 Programmable Logic Technologies 310 --<br/>6-6 Read-only Memory 312 --<br/>Combinational Circuit Implementation 315 --<br/>6-7 Programmable Logic Array 317 --<br/>6-8 Programmable Array Logic Devices 321 --<br/>6-9 VLSI Programmable Logic Devices 326 --<br/>Altera MAX 7000 CPLDs 326 --<br/>Xilinx XC4000 Structure 328 --<br/>Xilinx Interconnections 330 --<br/>Xilinx Logic 331 --<br/>Register Transfers and Datapaths 339 --<br/>7-1 Datapaths and Operations 340 --<br/>7-2 Register Transfer Operations 341 --<br/>A Note For VHDL And Verilog Users Only 344 --<br/>7-3 Microoperations 345 --<br/>Arithmetic Microoperations 345 --<br/>Logic Microoperations 347 --<br/>Shift Microoperations 349 --<br/>7-4 Multiplexer-based Transfer 350 --<br/>7-5 Bus-based Transfer 351 --<br/>Three-State Bus 353 --<br/>Memory Transfer 355 --<br/>7-6 Datapaths 357 --<br/>7-7 Arithmetic/Logic Unit 360 --<br/>Arithmetic Circuit 360 --<br/>Logic Circuit 363 --<br/>Arithmetic/Logic Unit 364 --<br/>7-8 Shifter 366 --<br/>Barrel Shifter 367 --<br/>7-9 Datapath Representation 368 --<br/>7-10 Control Word 370 --<br/>7-11 Pipelined Datapath 376 --<br/>Execution of Pipeline Microoperations 381 --<br/>Sequencing And Control 391 --<br/>8-1 Control Unit 392 --<br/>8-2 Algorithmic State Machines 393 --<br/>ASM Chart 393 --<br/>Timing Considerations 396 --<br/>8-3 Design Example: Binary Multiplier 397 --<br/>Binary Multiplier 397 --<br/>Multiplier Datapath 399 --<br/>ASM Chart for Multiplier 400 --<br/>8-4 Hardwired Control 402 --<br/>Sequence Register and Decoder 404 --<br/>One Flip-Flop per State 406 --<br/>8-5 HDL Representation of the Binary Multiplier --<br/>VHDL 410 --<br/>8-6 HDL Representation of the Binary Multiplier --<br/>Verilog 413 --<br/>8-7 Microprogrammed Control 416 --<br/>Binary Multiplier Example 418 --<br/>8-8 A Simple Computer Architecture 424 --<br/>Instructions 424 --<br/>Instruction Formats 425 --<br/>Storage Resource Diagram 428 --<br/>8-9 Single-Cycle Hardwired Control 429 --<br/>Instruction Decoder 431 --<br/>Sample Instructions and Program 433 --<br/>8-10 Multiple-Cycle Microprogrammed Control 437 --<br/>Microprogram Design 440 --<br/>Hardwired Alternative 447 --<br/>8-11 Pipelined Control 450 --<br/>Pipeline Programming and Performance 453 --<br/>Instruction Set Architecture 467 --<br/>9-1 Computer Architecture Concepts 467 --<br/>Basic Computer Operation Cycle 468 --<br/>Register Set 469 --<br/>9-2 Operand Addressing 469 --<br/>Three-address Instructions 470 --<br/>Two-address Instructions 471 --<br/>One-address Instructions 471 --<br/>Zero-address Instructions 472 --<br/>Addressing Architectures 473 --<br/>9-3 Addressing Modes 476 --<br/>Implied Mode 477 --<br/>Immediate Mode 477 --<br/>Register and Register-Indirect Modes 477 --<br/>Direct Addressing Mode 478 --<br/>Indirect Addressing Mode 480 --<br/>Relative Addressing Mode 480 --<br/>Indexed Addressing Mode 480 --<br/>Summary of Addressing Modes 481 --<br/>9-4 Instruction Set Architectures 482 --<br/>9-5 Data Transfer Instructions 484 --<br/>Stack Instructions 484 --<br/>Independent Versus Memory-Mapped I/O 486 --<br/>9-6 Data Manipulation Instructions 487 --<br/>Arithmetic Instructions 487 --<br/>Logical and Bit Manipulation Instructions 488 --<br/>Shift Instructions 490 --<br/>9-7 Floating-point Computations 491 --<br/>Arithmetic Operations 492 --<br/>Biased Exponent 493 --<br/>Standard Operand Format 493 --<br/>9-8 Program Control Instructions 495 --<br/>Conditional Branch Instructions 497 --<br/>Procedure Call and Return Instructions 499 --<br/>9-9 Program Interrupt 500 --<br/>Types of Interrupts 502 --<br/>Processing External Interrupts 503 --<br/>Central Processing Unit Designs 511 --<br/>10-1 Two CPU Designs 511 --<br/>10-2 Complex Instruction Set Computer 512 --<br/>Instruction Set Architecture 512 --<br/>Datapath Organization 517 --<br/>Microprogrammed Control Organization 523 --<br/>Microprogram Structure 531 --<br/>Microroutines 533 --<br/>10-3 Reduced Instruction Set Computer 542 --<br/>Instruction Set Architecture 542 --<br/>Addressing Modes 545 --<br/>Datapath Organization 546 --<br/>Control Organization 549 --<br/>Data Hazards 551 --<br/>Control Hazards 558 --<br/>10-4 More on Design 562 --<br/>CISC-RISC Comparison 562 --<br/>High-Performance CPU Concepts 564 --<br/>Recent Architectural Innovations 568 --<br/>Digital Systems 569 --<br/>Input-Output and Communication 575 --<br/>11-1 Computer I/O 575 --<br/>11-2 Sample Peripherals 576 --<br/>Keyboard 576 --<br/>Hard Disk 577 --<br/>Graphics Display 579 --<br/>I/O Transfer Rates 580 --<br/>11-3 I/O Interfaces 580 --<br/>I/O Bus and Interface Unit 581 --<br/>Example of I/O Interface 582 --<br/>Strobing 584 --<br/>Handshaking 585 --<br/>11-4 Serial Communication 587 --<br/>Asynchronous Transmission 588 --<br/>Synchronous Transmission 589 --<br/>Keyboard Revisited 589 --<br/>A Packet-Based Serial I/O Bus 590 --<br/>11-5 Modes of Transfer 594 --<br/>Example of Program-Controlled Transfer 595 --<br/>Interrupt-Initiated Transfer 596 --<br/>11-6 Priority Interrupt 598. |
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical Term | Electronic digital computers -- Circuits. |
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical Term | Logic circuits. |
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical Term | Logic design. |
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical Term | Logic programming. |
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical Term | Computer |
700 ## - ADDED ENTRY--PERSONAL NAME | |
Personal name | Kime, Charles R. ; |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | Reference Books |
Collection code | Home library | Current library | Shelving location | Date acquired | Source of acquisition | Cost, normal purchase price | Full call number | Accession Number | Koha item type |
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Reference | Main Library | Main Library | Reference | 23/01/2004 | Purchased | 812.50 | 004.2 MAN | 008240 | Reference Books |