TY - BOOK AU - Mano, M.Morris ; AU - Kime, Charles R. ; TI - Logic and computer design fundamentals SN - 0130124680 U1 - 004.2 PY - 2001/// CY - New Delhi PB - Pearson Education Asia KW - Electronic digital computers -- Circuits. KW - Logic circuits. KW - Logic design KW - Logic programming. KW - Computer N1 - Included Index; Digital Computers and Information 3 -- 1-1 Digital Computers 3 -- Information Representation 5 -- Computer Structure 6 -- More on the Generic Computer 6 -- 1-2 Number Systems 8 -- Binary Numbers 9 -- Octal and Hexadecimal Numbers 10 -- Number Ranges 12 -- 1-3 Arithmetic Operations 13 -- Conversion from Decimal to Other Bases 15 -- 1-4 Decimal Codes 17 -- BCD Addition 19 -- 1-5 Alphanumeric Codes 20 -- ASCII Character Code 20 -- Parity Bit 22 -- Combinational Logic Circuits 27 -- 2-1 Binary Logic and Gates 27 -- Binary Logic 28 -- Logic Gates 30 -- 2-2 Boolean Algebra 31 -- Basic Identities of Boolean Algebra 33 -- Algebraic Manipulation 35 -- Complement of a Function 38 -- 2-3 Standard Forms 39 -- Minterms and Maxterms 39 -- Sum of Products 43 -- Product of Sums 44 -- 2-4 Map Simplification 45 -- Two-Variable Map 46 -- Three-Variable Map 47 -- Four-Variable Map 52 -- 2-5 Map Manipulation 55 -- Essential Prime Implicants 55 -- Nonessential Prime Implicants 57 -- Product-of-Sums Simplification 58 -- Don't-Care Conditions 60 -- 2-6 Nand and Nor Gates 62 -- Nand Circuits 64 -- Two-Level Implementation 65 -- Multilevel Nand Circuits 67 -- Nor Circuits 69 -- 2-7 Exclusive-Or Gates 71 -- Odd Function 73 -- Parity Generation and Checking 74 -- 2-8 Integrated Circuits 76 -- Levels of Integration 76 -- Digital Logic Families 76 -- Positive and Negative Logic 79 -- Transmission Gates 81 -- Combinational Logic Design 91 -- 3-1 Combinational Circuits 91 -- 3-2 Design Topics 92 -- Design Hierarchy 93 -- Top-Down Design 96 -- Computer-Aided Design 96 -- Hardware Description Languages 97 -- Logic Synthesis 99 -- 3-3 Analysis Procedure 100 -- Derivation of Boolean Functions 101 -- Derivation of the Truth Table 102 -- Logic Simulation 103 -- 3-4 Design Procedure 105 -- Code Converters 107 -- 3-5 Decoders 111 -- Decoder Expansion 113 -- Combinational Circuit Implementation 114 -- 3-6 Encoders 116 -- Priority Encoder 117 -- 3-7 Multiplexers 119 -- Combinational Circuit Implementation 122 -- Demultiplexer 124 -- 3-8 Binary Adders 125 -- Half Adder 125 -- Full Adder 126 -- Binary Ripple Carry Adder 127 -- Carry Lookahead Adder 129 -- 3-9 Binary Subtraction 132 -- Complements 134 -- Subtraction with Complements 135 -- 3-10 Binary Adder-Subtractors 137 -- Singed Binary Numbers 138 -- Signed Binary Addition and Subtraction 140 -- Overflow 142 -- 3-11 Binary Multipliers 144 -- 3-12 Decimal Arithmetic 145 -- Use of Complements in Decimal 147 -- 3-13 HDL Representations -- VHDL 148 -- Structural Description 150 -- Dataflow Description 153 -- Hierarchical Description 155 -- Behavioral Description 157 -- 3-14 HDL Representations -- Verilog 159 -- Structural Description 160 -- Dataflow Description 161 -- Hierarchical Description 165 -- Behavioral Description 165 -- Sequential Circuits 183 -- 4-1 Sequential Circuit Definitions 184 -- 4-2 Latches 186 -- SR and S R Latches 187 -- D Latch 190 -- 4-3 Flip-Flops 191 -- Master-Slave Flip-Flop 192 -- Edge-Triggered Flip-Flop 195 -- Standard Graphics Symbols 197 -- Characteristic Tables 199 -- Direct Inputs 200 -- 4-4 Sequential Circuit Analysis 201 -- Input Equations 201 -- State Table 202 -- Analysis with JK Flip-Flops 206 -- State Diagram 206 -- 4-5 Sequential Circuit Design 208 -- Design Procedure 208 -- Finding State Diagrams and State Tables 209 -- 4-6 Designing with D Flip-Flops 214 -- Designing with Unused States 215 -- 4-7 Designing with JK Flip-Flops 218 -- Flip-Flop Excitation Tables 218 -- Design Procedure 219 -- 4-8 HDL Representation for Sequential Circuits -- VHDL 224 -- 4-9 HDL Representation for Sequential Circuits -- Verilog 232 -- Registers and Counters 249 -- 5-1 Definition of Register and Counter 249 -- 5-2a Registers 250 -- Register with Parallel Load 251 -- 5-3 Shift Registers 253 -- Serial Transfer 254 -- Serial Addition 256 -- Shift Register with Parallel Load 258 -- Bidirectional Shift Register 260 -- 5-4 Ripple Counter 261 -- 5-5 Synchronous Binary Counters 263 -- Design of Binary Counters 264 -- Counter with D Flip-Flops 267 -- Serial and Parallel Counters 268 -- Up-Down Binary Counter 269 -- Binary Counter with Parallel Load 270 -- 5-6 Other Counters 273 -- BCD Counter 273 -- Arbitrary Count Sequence 274 -- 5-7 HDL Representation for Shift Registers and Counters 276 -- 5-8 HDL Representation for Shift Registers and Counters 278 -- Memory and Programmable Logic Devices 285 -- 6-1 Memory and Programmable Logic Device 285 -- Definitions 286 -- 6-2 Random-access Memory 287 -- Write and Read Operations 289 -- Timing Waveforms 290 -- Properties of Memory 292 -- 6-3 RAM Integrated Circuits 292 -- Three-State Buffers 296 -- Coincident Selection 297 -- Dynamic RAM ICs 301 -- 6-4 Array of RAM ICs 307 -- Arrays of Dynamic RAM ICs 310 -- 6-5 Programmable Logic Technologies 310 -- 6-6 Read-only Memory 312 -- Combinational Circuit Implementation 315 -- 6-7 Programmable Logic Array 317 -- 6-8 Programmable Array Logic Devices 321 -- 6-9 VLSI Programmable Logic Devices 326 -- Altera MAX 7000 CPLDs 326 -- Xilinx XC4000 Structure 328 -- Xilinx Interconnections 330 -- Xilinx Logic 331 -- Register Transfers and Datapaths 339 -- 7-1 Datapaths and Operations 340 -- 7-2 Register Transfer Operations 341 -- A Note For VHDL And Verilog Users Only 344 -- 7-3 Microoperations 345 -- Arithmetic Microoperations 345 -- Logic Microoperations 347 -- Shift Microoperations 349 -- 7-4 Multiplexer-based Transfer 350 -- 7-5 Bus-based Transfer 351 -- Three-State Bus 353 -- Memory Transfer 355 -- 7-6 Datapaths 357 -- 7-7 Arithmetic/Logic Unit 360 -- Arithmetic Circuit 360 -- Logic Circuit 363 -- Arithmetic/Logic Unit 364 -- 7-8 Shifter 366 -- Barrel Shifter 367 -- 7-9 Datapath Representation 368 -- 7-10 Control Word 370 -- 7-11 Pipelined Datapath 376 -- Execution of Pipeline Microoperations 381 -- Sequencing And Control 391 -- 8-1 Control Unit 392 -- 8-2 Algorithmic State Machines 393 -- ASM Chart 393 -- Timing Considerations 396 -- 8-3 Design Example: Binary Multiplier 397 -- Binary Multiplier 397 -- Multiplier Datapath 399 -- ASM Chart for Multiplier 400 -- 8-4 Hardwired Control 402 -- Sequence Register and Decoder 404 -- One Flip-Flop per State 406 -- 8-5 HDL Representation of the Binary Multiplier -- VHDL 410 -- 8-6 HDL Representation of the Binary Multiplier -- Verilog 413 -- 8-7 Microprogrammed Control 416 -- Binary Multiplier Example 418 -- 8-8 A Simple Computer Architecture 424 -- Instructions 424 -- Instruction Formats 425 -- Storage Resource Diagram 428 -- 8-9 Single-Cycle Hardwired Control 429 -- Instruction Decoder 431 -- Sample Instructions and Program 433 -- 8-10 Multiple-Cycle Microprogrammed Control 437 -- Microprogram Design 440 -- Hardwired Alternative 447 -- 8-11 Pipelined Control 450 -- Pipeline Programming and Performance 453 -- Instruction Set Architecture 467 -- 9-1 Computer Architecture Concepts 467 -- Basic Computer Operation Cycle 468 -- Register Set 469 -- 9-2 Operand Addressing 469 -- Three-address Instructions 470 -- Two-address Instructions 471 -- One-address Instructions 471 -- Zero-address Instructions 472 -- Addressing Architectures 473 -- 9-3 Addressing Modes 476 -- Implied Mode 477 -- Immediate Mode 477 -- Register and Register-Indirect Modes 477 -- Direct Addressing Mode 478 -- Indirect Addressing Mode 480 -- Relative Addressing Mode 480 -- Indexed Addressing Mode 480 -- Summary of Addressing Modes 481 -- 9-4 Instruction Set Architectures 482 -- 9-5 Data Transfer Instructions 484 -- Stack Instructions 484 -- Independent Versus Memory-Mapped I/O 486 -- 9-6 Data Manipulation Instructions 487 -- Arithmetic Instructions 487 -- Logical and Bit Manipulation Instructions 488 -- Shift Instructions 490 -- 9-7 Floating-point Computations 491 -- Arithmetic Operations 492 -- Biased Exponent 493 -- Standard Operand Format 493 -- 9-8 Program Control Instructions 495 -- Conditional Branch Instructions 497 -- Procedure Call and Return Instructions 499 -- 9-9 Program Interrupt 500 -- Types of Interrupts 502 -- Processing External Interrupts 503 -- Central Processing Unit Designs 511 -- 10-1 Two CPU Designs 511 -- 10-2 Complex Instruction Set Computer 512 -- Instruction Set Architecture 512 -- Datapath Organization 517 -- Microprogrammed Control Organization 523 -- Microprogram Structure 531 -- Microroutines 533 -- 10-3 Reduced Instruction Set Computer 542 -- Instruction Set Architecture 542 -- Addressing Modes 545 -- Datapath Organization 546 -- Control Organization 549 -- Data Hazards 551 -- Control Hazards 558 -- 10-4 More on Design 562 -- CISC-RISC Comparison 562 -- High-Performance CPU Concepts 564 -- Recent Architectural Innovations 568 -- Digital Systems 569 -- Input-Output and Communication 575 -- 11-1 Computer I/O 575 -- 11-2 Sample Peripherals 576 -- Keyboard 576 -- Hard Disk 577 -- Graphics Display 579 -- I/O Transfer Rates 580 -- 11-3 I/O Interfaces 580 -- I/O Bus and Interface Unit 581 -- Example of I/O Interface 582 -- Strobing 584 -- Handshaking 585 -- 11-4 Serial Communication 587 -- Asynchronous Transmission 588 -- Synchronous Transmission 589 -- Keyboard Revisited 589 -- A Packet-Based Serial I/O Bus 590 -- 11-5 Modes of Transfer 594 -- Example of Program-Controlled Transfer 595 -- Interrupt-Initiated Transfer 596 -- 11-6 Priority Interrupt 598 ER -